Novel N-hit single event transient mitigation technique via open guard transistor in 65nm bulk CMOS process
Author:
Publisher
Springer Science and Business Media LLC
Subject
General Engineering,General Materials Science
Link
http://link.springer.com/content/pdf/10.1007/s11431-012-5070-8.pdf
Reference19 articles.
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2. Olson B D, Amusan O A, Dasgupta S, et al. Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology. IEEE Trans Nucl Sci,. 2007, 54(4): 894–897
3. Amusan O A, Massengill L W, Bhuva B L, et al. Design techniques to reduce SET pulse widths in deep-submicron combinational logic. IEEE Trans Nucl Sci, 2007, 54(6): 2060–2064
4. Roy T, Witulski A F, Schrimpf R D, et al. Single event mechanisms in 90 nm triple-well CMOS devices. IEEE Trans Nucl Sci, 2008, 55(6): 2948–2956
5. Chen J J, Chen S M, Liang B, et.al. Single event transient pulse attenuation effect in three-transistor inverter chain. Sci China Tech Sci, 2012, 55: 867–871
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