Hierarchical test analysis of VLSI circuits for random BIST
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-58426-9_136.pdf
Reference11 articles.
1. M. S. Abadir, M. A. Breuer: A knowledge-based system for designing testable VLSI chips. IEEE Design and Test, pp. 56–68 (1985)
2. P. N. Anirudhan, P. R. Menon: Symbolic test generation for hierarchically modeled digital systems. ITC, pp. 461–469 (1989)
3. M. A. Breuer, A. D. Friedman: Functional level primitives in test generation. IEEE Transactions on Computers, pp. 223–235 (1980)
4. R. David, G. Blanchet: About random fault detection of combinational networks. IEEE Transactions on Computers, pp. 650–664 (1976)
5. S. Freeman: Test generation for data path logic: the F-path method. IEEE Journal of Solid-State Circuits, vol. 23, nℴ2, pp. 421–427 (1988)
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