Combining CTL, trace theory and timing models
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/3-540-52148-8_28.pdf
Reference12 articles.
1. David L. Black. On the existence of fair delay-insensitive arbiters: trace theory and its limitations. Distributed Computing, 1(4):205–225, 1986.
2. M. C. Browne, E. M. Clarke, D. L. Dill, and B. Mishra. Automatic verification of sequential circuits using temporal logic. IEEE Transactions on Computers, C-35(12):1035–1044, 1986.
3. Jerry R. Burch. The design of a delay-insensitive fair mutual exclusion circuit. In Preparation.
4. E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems, 8(2):244–263, 1986.
5. David L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. PhD thesis, Department of Computer Science, Carnegie Mellon University, 1988.
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