Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application-Reference-Cited by-同舟云学术

Quad-level cell NAND design and soft-bit generation for low-density parity-check decoding in system-level application

Published:2018-01-13 Issue:1 Volume:23 Page:70-78
ISSN:1007-1202
Container-title:Wuhan University Journal of Natural Sciences
language:en
Short-container-title:Wuhan Univ. J. Nat. Sci.

Author:

Liu Shijun,Zou Xuecheng,Wang Baocun

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://link.springer.com/article/10.1007/s11859-018-1296-z/fulltext.html

Reference21 articles.

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2. Kang D, Jeong W, Kim C, et al. 256Gb 3 b/cell V-NAND flash memory with 48 stacked WL layers[C] // IEEE International Solid-State Circuits Conference. New York: IEEE, 2016: 130–132.

3. Aritome S. NAND Flash memory revolution[C] // IEEE 8th International Memory Workshop. New York: IEEE, 2016: 1–4.

4. Lai S. Non-volatile memory technologies: The quest for ever lower cost[C] // IEEE International Electron Devices Meeting. New York: IEEE, 2008: 1–6.

5. Lim J Y, Moon P, Lee S M, et al. Analysis of intrinsic charge loss mechanisms for nanoscale NAND flash memory[J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(3): 319–325.

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