Experimental study of temperature dependence of single-event upset in SRAMs-Reference-Cited by-同舟云学术

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Experimental study of temperature dependence of single-event upset in SRAMs

Published:2016-02 Issue:1 Volume:27 Page:
ISSN:1001-8042
Container-title:Nuclear Science and Techniques
language:en
Short-container-title:NUCL SCI TECH

Author:

Cai Li,Guo Gang,Liu Jian-Cheng,Fan Hui,Shi Shu-Ting,Wang Hui,Wang Gui-Liang,Shen Dong-Jun,HUI Ning,He An-Lin

Publisher

Springer Science and Business Media LLC

Subject

Nuclear Energy and Engineering,Nuclear and High Energy Physics

Link

http://link.springer.com/content/pdf/10.1007/s41365-016-0014-9.pdf

Reference17 articles.

1. W.A. Kolasinski, R. Koga, E. Schnauss et al., The effect of elevated temperature on latchup and bit errors in CMOS devices. IEEE Trans. Nucl. Sci. 33, 1605–1609 (1986). doi: 10.1109/TNS.1986.4334649

2. J.S. Larid, T. Hirao, S. Onoda et al., Temperature dependency of heavy ion induced current transients in Si epilayer devices. IEEE Trans. Nucl. Sci. 49, 1389–1395 (2002). doi: 10.1109/RADECS.2001.1159269

3. M.S. Copper, J.P. Retzler, G.C. Messenger, High temperature Schottky TTL latchup. IEEE Trans. Nucl. Sci. 25, 1538–1544 (1978). doi: 10.1109/TNS.1978.4329568

4. A.H. Johnston, B.H. Hughlock, M.P. Baze et al., The effect of temperature on single-particle latchup. IEEE Trans. Nucl. Sci. 38, 1435–1441 (1991). doi: 10.1109/23.124129

5. W.J. Stapor, P.T. McDonald, S.L. Swickert et al., Low temperature proton induced upsets in NMOS resistive load static RAM. IEEE Trans. Nucl. Sci. 35, 1596–1601 (1988). doi: 10.1109/23.25504

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4. Single event upset for monolithic 3-D integrated 6T SRAM based on a 22 nm FD-SOI technology: Effects of channel size and temperature;Microelectronics Reliability;2020-11

5. Experimental investigation of SEUs Induced by Heavy Ions in 28-nm FDSOI SRAMs;2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS);2019-09

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