On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture-Reference-Cited by-同舟云学术

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On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture

Published:2013 Issue: Volume: Page:155-165
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Alidash Hossein Karimiyan,Calimera Andrea,Macii Alberto,Macii Enrico,Poncino Massimo

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-36157-9_16.pdf

Reference23 articles.

1. Paul, B.C., Kang, K., Kufluoglu, H., Alam, M.A., Roy, K.: Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron. Device Letters 26(8), 560–562 (2005)

2. Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., Vrudhula, S.: Predictive Modeling of the NBTI Effect for Reliable Design. In: IEEE CICC 2006, pp. 189–192 (2006)

3. Scarpa, A., Ward, D., Dubois, J., van Marwijk, L., Gausepohl, S., Campos, R., Sim, K.Y., Cacciato, A., Kho, R., Bolt, M.: Negative-bias temperature instability cure by process optimization. IEEE Tran. on Electron. Devices 53(6), 1331–1339 (2006)

4. Basu, S., Vemuri, R.: Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. In: Proc. of the IEEE ISVLSI 2007, pp. 291–298 (2007)

5. Yang, X., Saluja, K.: Combating NBTI Degradation via Gate Sizing. In: Proc. of the 8th Inte.l Symp. on Quality Electronic Design (ISQED 2007), pp. 47–52. IEEE Computer Soc. (2007)

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1. Circuit Techniques for BTI and EM Accelerated and Active Recovery;Circadian Rhythms for Future Resilient Electronic Systems;2019-06-13

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