Comparing the Performance Parameters of Network on Chip with Regular and Irregular Topologies
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-22543-7_18
Reference13 articles.
1. Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35(1), 70–78 (2002)
2. Chang, K.-C., Chen, T.-F.: Low-power algorithm for automatic topology generation for application-specific networks on chips. IET Comput. Digit. Tech. 2(3), 239–249 (2008)
3. Dally, W.J., Towles, B.: Route packets and not wires: on-chip interconnection networks. In: Proc. Design and Automation Conf., pp. 684–689 (2001)
4. Henkel, J., Wolf, W., Chakradhar, S.: On-chip networks: A scalable and communication-centric embedded system design paradigm. In: 17th International Conference on VLSI Design (2004)
5. Verdoscia, L., Roberto Vaccaro Istituto per la, Ricerca sui Sistemi Informatici, Paralleli CNR Via P. Castellino, 111 80131 Napoli-Italy: An Adaptive Routing Algorithm for WK-Recursive Topologies. Source Computing Journal 63 (1999)
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