Design Methodology of Dynamically Reconfigurable Network-on-Chip
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-21762-3_14.pdf
Reference7 articles.
1. Devaux, L., Sassi, S.B., et al.: Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. International Journal of Reconfigurable Computing (2010)
2. Bobda, C., Ahmadinia, A., Majer, M., Teich, J., Fekete, S., Veen, J.v.d.: DyNoC: a dynamic infrastructure for communicationin dynamically reconfigurable devices. In: Proceedingsof the International Conference on Field Programmable Logicand Applications (FPL 2005), Tampere,Finland, pp. 153–158 (August 2005)
3. Pionteck, T., Koch, R., Albrecht, C.: Applying partial reconfiguration to networks-onchips. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 06), pp. 155–160, Madrid, Spain (August 2006)
4. Jovanovic, S., Tanougast, C., et al.: CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs. Microprocessors and Microsystems 33, 24–36 (2009)
5. Gu, H., Li, C., Sunshu: Research on Mapping Algorithm of irregular mesh NoC for Portable Multimedia Appliances. In: CCWMSN 2007 (2007)
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