A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-24270-0_24
Reference27 articles.
1. Reinhardt, S.K., Mukherjee, S.S.: Transient-Fault Detection via Simultaneous Multithreading. In: The Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA 2000), Canada, pp. 25–36 (June 2000)
2. Gibson, D., Wood, D.A.: Forward flow: a Scalable Core for Power-Constrained CMPs. In: The Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA 2010), USA, pp. 1–12 (June 2010)
3. Bhattacharjee, A., Martonosi, M.: Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors. In: Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA 2009), USA, pp. 290–301 (June 2009)
4. Sanchez, D., Aragon, J.L., Garcia, J.M.: Extending SRT for Parallel Applications in Tiled-CMP Architecture. In: The Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing (IPDPS 2009), USA, pp. 1–8 (July 2009)
5. Prvulovic, M., Zhang, Z., Torrellas, J.: ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. In: The Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA 2002), USA, pp. 111–122 (May 2002)
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