Author:
Jayagowri R.,Gurumurthy K. S.
Publisher
Springer Berlin Heidelberg
Reference13 articles.
1. Zorian, Y.: A distributed BIST control scheme for complex VLSI devices. In: IEEE VLSI Test Symposium, pp. 4–9 (1993)
2. Dobholkar, V., et al.: Techniques to minimize power dissipation in scan and combinational circuits during test application. IEEE Transactions on Computer Aided Design, 1325–1333 (December 1998)
3. Kajihara, S., et al.: Test vector modification for power reduction during scan testing. In: Proceedings VLSI Test Symposium (2002)
4. Ramersaro, et al.: Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. In: International Test Conference, pp. 1–10 (2006)
5. Gerstendorfer, S., Wunderlich, H.J.: Minimized power consumption for scan based BIST. In: Proceeding International Test Conference (1999)
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