Robust Adaptation to Available Parallelism in Transactional Memory Applications-Reference-Cited by-同舟云学术

Robust Adaptation to Available Parallelism in Transactional Memory Applications

Published:2011 Issue: Volume: Page:236-255
ISSN:0302-9743
Container-title:Transactions on High-Performance Embedded Architectures and Compilers III
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Author:

Ansari Mohammad,Luján Mikel,Kotselidis Christos,Jarvis Kim,Kirkham Chris,Watson Ian

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-19448-1_13

Reference25 articles.

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3. Kongetira, P., Aingaran, K., Olukotun, K.: Niagara: A 32-way multithreaded sparc processor. IEEE Micro 25(2), 21–29 (2005)

4. McDougall, R.: Extreme software scaling. ACM Queue 3(7), 36–46 (2005)

5. Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: ISCA 1993: Proceedings of the 20th Annual International Symposium on Computer Architecture, pp. 289–300 (May 1993)

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