1. International Technology Roadmap for Semiconductors,
http://public.itrs.net/
2. Martin, A.J.: The limitations to delay-insensitivity in asynchronous circuits. In: Dally, W.J. (ed.) Advanced Research in VLSI, pp. 263–278. MIT Press, Cambridge (1990)
3. Sylvester, D., Agarwal, K., Shah, S.: Variability in nanometer CMOS: Impact, analysis, and minimization. Integration the VLSI Journal 41, 319–339 (2008)
4. Roy, S., et al.: Impact of intrinsic parameter fluctuations in nano-CMOS devices on circuits and systems. In: Ryzhii, M., Ryzhii, V. (eds.) Physics and Modeling of Tera- and Nano-Devices. World Scientific, NY (2008)
5. Saito, H., Kondratyev, A., Cortadella, J., Lavagno, L., Yakovlev, A.: What is the cost of delay insensitivity? In: Proc. ICCAD 1999, San Jose, CA, November 1999, pp. 316–323 (1999)