Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA

Author:

Ma Yuan,Xia Luning,Lin Jingqiang,Jing Jiwu,Liu Zongbin,Yu Xingjie

Publisher

Springer Berlin Heidelberg

Reference10 articles.

1. Chinese Commercial Cryptography Administration Office: Sepecification of SM3 Cryptographic Hash Function (2010) (in Chinese), http://www.oscca.gov.cn/UpFile/20101222141857786.pdf

2. HELION: Fast SHA-256 core for xilinx FPGA (2011), http://www.helion.com/

3. Lecture Notes in Computer Science;R. Chaves,2006

4. McEvoy, R.P., Crowe, F.M., Murphy, C.C., Marnane, W.P.: Optimisation of the SHA-2 Family of Hash Functions on FPGAs. In: IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), pp. 317–322 (2006)

5. Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Cost-Efficient SHA Hardware Accelerators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8), 999–1008 (2008)

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