Author:
Tsirogiannis Elias,Theodoropoulos Georgios
Publisher
Springer Berlin Heidelberg
Reference32 articles.
1. Bailey, M.L., Briner, J.V., Chamberlain, R.D.: Parallel Logic Simulation of VLSI Systems. ACM Computing Surveys (CSUR) 26(3), 255–294 (1994)
2. Barnard, S.T., Simon, H.D.: A Fast Multilevel Implementation of Recursive Spectral Bisection for Partitioning Unstructured Problems. In: 6th SIAM Conference on Parallel Processing for Scientific Computing, pp. 711–718 (March 1993)
3. Bui, T.N., Jones, C.: A Heuristic for Reducing Fill in Sparse Matrix Factorization. In: 6th SIAM Conference on Parallel Processing for Scientific Computing. pp. 445–452. SIAM (March 1993)
4. Cong, J., Smith, M.: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. In: 30th Design Automation Conference, pp. 755–760. ACM/IEEE (June 1993)
5. Diekmann, R., Monien, B., Preis, R.: Using Helpful Sets to Improve Graph Bisections. In: Interconnection Networks and Mapping and Scheduling Parallel Computations. DIMACS Series in Discrete Mathematics and Theoretical Computer Science, vol. 21, pp. 57–73. AMS (1995)
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