Author:
Huddar Sushma R.,Rupanagudi Sudhir Rao,Janardhan Venkatesh,Mohan Surabhi,Sandya S.
Publisher
Springer Berlin Heidelberg
Reference12 articles.
1. Arrathoon, R., Kozaitis, S.: Architectural and performance considerations for a 107-instruction/sec optoelectronic central processing unit. Optics Letters 12(11), 956–958 (1987)
2. Zhang, H., Wang, Z.-Q., Leu, W., Tan, Z.: The Design of Arithmetic Logic Unit based on ALM
3. Patterson, H.: Computer Organization and Design, 4th Revised edn., pp. 220–230. Morgan Kaufmann (2011)
4. Sriraman, L., Prabakar, T.N.: Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics. In: 1st International Conference on Recent Advances in Information Technology. IEEE (2012)
5. Booth, A.D.: A Signed Binary Multiplication Technique. J. Mech. Appl. Math. 4, 236–240 (1951)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24