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Unifying Thread-Level Speculation and Transactional Memory

Published:2012 Issue: Volume: Page:187-207
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Barreto João,Dragojevic Aleksandar,Ferreira Paulo,Filipe Ricardo,Guerraoui Rachid

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-35170-9_10

Reference31 articles.

1. Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: 25 Years of the International Symposia on Computer Architecture (selected papers), ISCA 1998, pp. 521–532. ACM, New York (1998)

2. Hammond, L., Willey, M., Olukotun, K.: Data speculation support for a chip multiprocessor. SIGPLAN Not. 33, 58–69 (1998)

3. Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: Proceedings of the 20th Annual International Symposium on Computer Architecture (1993)

4. Oancea, C.E., Mycroft, A., Harris, T.: A lightweight in-place implementation for software thread-level speculation. In: Proceedings of the Twenty-First Annual Symposium on Parallelism in Algorithms and Architectures, pp. 223–232 (2009)

5. Dragojević, A., Felber, P., Gramoli, V., Guerraoui, R.: Why stm can be more than a research toy. Commun. ACM 54(4), 70–77 (2011)

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