Lerna

Author:

Saad Mohamed M.1,Palmieri Roberto2,Ravindran Binoy3

Affiliation:

1. Alexandria University, Alexandria, Egypt

2. Lehigh University, Bethlehem, PA, USA

3. Virginia Tech Blacksburg, VA, USA

Funder

Air Force Office of Scientific Research

Publisher

ACM

Reference57 articles.

1. {n. d.}. Intel Parallel Studio. ({n. d.}). https://software.intel.com/\en-us/intel-parallel-studio-xe. {n. d.}. Intel Parallel Studio. ({n. d.}). https://software.intel.com/\en-us/intel-parallel-studio-xe.

2. {n. d.}. RSTM: The University of Rochester STM. ({n. d.}). www.cs.rochester.edu/research/synchronization/\rstm/. {n. d.}. RSTM: The University of Rochester STM. ({n. d.}). www.cs.rochester.edu/research/synchronization/\rstm/.

3. Transactional memory with strong atomicity using off-the-shelf memory protection hardware

4. Alfred V Aho Jeffrey D Ullman etal 1977. Principles of compiler design. Addision-Wesley Pub. Co. Alfred V Aho Jeffrey D Ullman et al. 1977. Principles of compiler design. Addision-Wesley Pub. Co.

5. Adaptive optimization in the Jalapeño JVM

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Ordered scheduling in control-flow distributed transactional memory;Theoretical Computer Science;2024-04

2. Ordered Scheduling in Control-Flow Distributed Transactional Memory;Lecture Notes in Computer Science;2023

3. Processing Distributed Transactions in a Predefined Order;International Conference on Distributed Computing and Networking 2021;2021-01-05

4. Processing transactions in a predefined order;Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming;2019-02-16

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