Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models

Author:

Raffelsieper Matthias,Mousavi MohammadReza,Roorda Jan-Willem,Strolenberg Chris,Zantema Hans

Publisher

Springer Berlin Heidelberg

Reference8 articles.

1. IEEE Std 1364-2005: IEEE Standard for Verilog Hardware Description Language. IEEE Computer Society Press, Los Alamitos (2006)

2. Baader, F., Nipkow, T.: Term Rewriting and All That. Cambridge University Press, Cambridge (1998)

3. Lecture Notes in Computer Science;A. Cimatti,2002

4. Lecture Notes in Computer Science;C. Helmstetter,2007

5. Helmstetter, C., Maraninchi, F., Maillet-Contoz, L., Moy, M.: Automatic generation of schedulings for improving the test coverage of Systems-on-a-Chip. In: Proceedings of FMCAD 2006, pp. 171–178. IEEE Computer Society Press, Los Alamitos (2006)

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1. Formal Analysis of SystemC Designs in Process Algebra;Fundamenta Informaticae;2011

2. Long-run order-independence of vector-based transition systems;IET Computers & Digital Techniques;2011

3. Symbolic Power Analysis of Cell Libraries;Formal Methods for Industrial Critical Systems;2011

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