High Speed Flexible Pairing Cryptoprocessor on FPGA Platform
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-17455-1_28
Reference31 articles.
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3. Ghosh, S., Mukhopadhyay, D., Roychowdhury, D.: High Speed F p Multipliers and Adders on FPGA Platform. In: DASIP 2010, Scotland (2010)
4. Beuchat, J.L., Díaz, J.E.G., Mitsunari, S., Okamoto, E., Henríquez, F.R., Teruya, T.: High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves. Cryptology ePrint Archive, Report 2010/354, http://eprint.iacr.org/
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