Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://link.springer.com/article/10.1007/s11277-017-5036-z/fulltext.html
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3. Haraszti, T. (2000). CMOS memory circuits. Boston: Kluwer Academic.
4. Sakode, V., Lombardi, F., & Han, J. (2012). Cell design and comparative evaluation of a novel 1T memristor-based memory. In Proceedings of the 2012 IEEE/ACM international symposium on nanoscale architectures—NANOARCH ‘12.
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