Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4489831/4497639/04497686.pdf?arnumber=4497686
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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4. Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology;International Journal of Circuits, Systems and Signal Processing;2021-07-28
5. FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm;International Journal of Circuits, Systems and Signal Processing;2021-07-22
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