Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application-Reference-Cited by-同舟云学术

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Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application

Published:2022-01-31 Issue:2 Volume:123 Page:1573-1591
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Nejadhasan Sajad,Mehrabi-Moghadam Zahra,Abiri Ebrahim,Salehi Mohammad Reza

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://link.springer.com/content/pdf/10.1007/s11277-021-09201-9.pdf

Reference22 articles.

1. Ghorbani, A., & Ghaznavi-Ghoushchi, M. (2017). A novel fully differential CMOS Class-E power amplifier with higher output power and efficiency for IoT application. Wireless Personal Communications, 97(2), 3203–3213.

2. Singh, M. K., & Akashe, S. (2018). Design and enactment of diverse low power techniques based schmitt trigger. Wireless Personal Communications, 101(4), 2105–2125.

3. Nejadhasan, S., Zaheri, F., Abiri, E., & Salehi, M. R. (2020). PVT-compensated low-voltage and low-power CMOS LNA for IoT applications. International Journal of RF and Microwave Computer-Aided Engineering, 30(11), e22419. https://doi.org/10.1002/mmce.22419.

4. Nejadhasan, S., Zaheri, F., Abiri, E., & Salehi, M. R. (2022). PVT-compensated low voltage LNA based on variable current source for low power applications. AEU - International Journal of Electronics and Communications, 143, 154042. https://doi.org/10.1016/j.aeue.2021.154042.

5. Ghanavati, B., Abiri, E., Salehi, M. R., Keyhani, A., & Sanyal, A. (2017). LSB split capacitor SAR ADC with 99.2% switching energy reduction. Analog Integrated Circuits and Signal Processing, 93(2), 375–382.

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1. Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications;Circuits, Systems, and Signal Processing;2024-08-13

2. Design and Analysis of SAR-ADC for Low Power Circuits;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

3. Design and Analysis of Low Power and High-Speed Dynamic Comparator with Transconductance Enhanced in Latching Stage for ADC Application;Journal of Circuits, Systems and Computers;2024-02-19

4. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15

5. Equivalent Number of Bits of Major ADC Types Considering the Evaluation of Their Dynamic Error;2023 5th International Youth Conference on Radio Electronics, Electrical and Power Engineering (REEPE);2023-03-16

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