P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA-Reference-Cited by-同舟云学术

P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA

Published:2020-06-19 Issue:4 Volume:114 Page:3295-3319
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Parane Khyamling^ORCID,Prabhu Prasad B. M.,Talawar Basavaraj

Funder

Ministry of Electronics and Information Technology, Government of India

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://link.springer.com/content/pdf/10.1007/s11277-020-07529-2.pdf

Reference27 articles.

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2. Bell, S., Edwards, B., Amann, J., Conlin, R., Joyce, K., Leung, V., et al. (2008). TILE64-processor: A 64-core SoC with mesh interconnect. In 2008 IEEE international solid-state circuits conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3–7, 2008, pp. 88–89.

3. Dally, W. J., & Towles, B. (2001). Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th design automation conference, DAC 2001, Las Vegas, NV, USA, June 18–22, 2001, pp. 684–689.

4. Kumar, S., Jantsch, A., Millberg, M., Öberg, J., Soininen, J., Forsell, M., et al. (2002). A network on chip architecture and design methodology. In2002 IEEE computer society annual symposium on VLSI (ISVLSI 2002), 25–26 April 2002 (pp. 117–124). PA, USA: Pittsburgh.

5. Papamichael, M., & Hoe, J. C. (2012). CONNECT: Re-examining conventional wisdom for designing NoCs in the context of FPGAS. In Proceedings of the ACM/SIGDA 20th international symposium on field programmable gate arrays, FPGA 2012, Monterey, California, USA, February 22–24, 2012, pp. 37–46.

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