1. Ali, M., Welzl, M., Hessler, S., & Hellebrand, S. (2007). A fault tolerant mechanism for handling permanent and transient failures in a network on chip. In: Proceedings of the 4th international conference on information technology-new generations, Las Vegas, NV (pp. 1027–1032).
2. Bahirat, S., & Pasricha, S. (2016). A software framework for rapid application-specific hybrid photonic network-on-chip synthesis. MDPI Electronics,
5(2), 1–24.
3. Chawade, S. D., Gaikwad, M. A., & Patrikar, R. M. (2012). Review of XY routing algorithm for network-on-chip architecture. International Journal of Computer Applications,
43(21), 20–24.
4. Chemli, B., & Zitouni, A. (2014). A turn model based router design for 3D network on chip. World Applied Sciences Journal,
32(8), 1499–1505.
5. Chtourou, S., Marrakchi, Z., Pangracious, V., Amouri, E., Mehrez, H., & Abid, M. (2015). Mesh of clusters FPGA architectures: exploration methodology and interconnect optimization. In: K. Sano, D. Soudris, M. Hübner, & P. Diniz (Eds.), Applied reconfigurable computing. ARC 2015. Lecture Notes in Computer Science (Vol. 9040). Cham: Springer.