An Advanced Encryption Standard in Memory (AESIM) Efficient, High Performance S-box Based AES Encryption and Decryption Architecture on VLSI-Reference-Cited by-同舟云学术

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An Advanced Encryption Standard in Memory (AESIM) Efficient, High Performance S-box Based AES Encryption and Decryption Architecture on VLSI

Published:2021-10-29 Issue: Volume: Page:
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Padmavathi R. Anusha^ORCID,Dhanalakshmi K. S.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://link.springer.com/content/pdf/10.1007/s11277-021-09278-2.pdf

Reference28 articles.

1. Tsai, K.-L., Leu, F.-Y., You, I., Chang, S.-W., Hu, S.-J., & Park, H. (2019). Low-Power AES Data Encryption Architecture for a LoRaWAN. IEEE Access, 7, 146348–146357.

2. Khan, S., Wilkerson, C., Lee, D., Alameldeen, A. R., & Mutlu, O. (2016). A case for memory content-based detection and mitigation of data-dependent failures in DRAM. IEEE Computer Architecture Letters, 16, 88–93.

3. Sai, R. V., Upadhyay, H. N., Prabhu, M., & Saravanan, S. (2019). Undeviating adaptive sheltered cryptography (UASC) method based low power and high secure cache memory design. Microprocessors and Microsystems., 71, 102876.

4. Chen, Z., Pappas, N., & Kountouris, M. (2016). Probabilistic caching in wireless D2D networks: cache hit optimal versus throughput optimal. IEEE Communications Letters, 21, 584–587.

5. N. Nishikawa, H. Amano, and K. Iwai. 2017. "Implementation of bitsliced AES encryption on CUDA-enabled GPU," In International Conference on Network and System Security, Springer. 273-287

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1. A VLSI Perspective on Encryption Algorithm Analysis;2024 International Conference on Communication, Computing and Internet of Things (IC3IoT);2024-04-17

2. Enabling PIM-based AES encryption for online video streaming;Journal of Systems Architecture;2022-11

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