Author:
Shylu D. S.,Moni D. Jackuline,Nivetha G.
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Reference27 articles.
1. Nagaraj, K., Singhal, K., Viswauathan, T. R., & Vlach, J. (2005). Reduction of the finite gain effect in switched-capacitor filters. Electronics Letters, 21, 644–645.
2. Li, J., & Moon, U. K. (2004). A 1.8 V 67 mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique. IEEE Journal of Solid-State Circuits, 39(9), 1468–1476.
3. Gregoire, B. R., & Moon, U. K. (2008). An over-60 dB true rail-to-rail performance using correlated level shifting and an op-amp with only 30 dB loop gain. IEEE Journal of Solid-State Circuits, 43(12), 2620–2630.
4. Koo, Y.-J., Li, J., Lee, B. & Moon, U.-K. (2007). Low-power and high-speed pipelined ADC using time-aligned CDS technique. In IEEE custom intergrated circuits conference (CICC) (pp. 321–324)
5. Lin, J.-F., Chang, S.-J., Liu, C.-C., & Huang, C.-H. (2010). A 10-bit 60 MS/s low power pipelined ADC with split capacitor CDS technique. IEEE Transactions on Circuits and Systems II, Express Briefs, 57(3), 163–167.
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