Quantum Mechanical Effect on Trigate Junctionless FET for Fast Switching Application

Author:

Prasad M.ORCID,Mahadevaswamy U. B.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Reference15 articles.

1. Baruah, R. K., & Paily, R. P. (2015). The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor. Journal of Computational Electronics, 14(2), 492–499.

2. Barraud, S., Lapras, V., Previtali B., Samson MP., Lacord J., Martinie S., & Ernst, T. (2017). Performance and design considerations for gate-all-around stacked-NanoWires FETs. In 2017 IEEE international electron devices meeting (IEDM).

3. Young et al., C.D. (2011). Critical discussion on (100) and (110) orientation dependent transport: nMOS Planar and FinFET. In 2011 symposium on VLSI technology digest of technical papers.

4. Entner, R., Gehring, A., Grasser, T., & Selberherr, S. (2004). A comparison of quantum correction models for the three-dimensional simulation of FinFET structures. In 27th international spring seminar on electronics technology: Meeting the challenges of electronics technology progress.

5. Jeong, E.-Y., et al. (2015). Investigation of RC parasitics considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm node logic applications. IEEE Transactions on Electron Devices, 62(10), 3441.

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2. Performance analysis of stacked Nano sheet at gate length of 10nm at linear and saturation region;2023 International Conference on Computer Communication and Informatics (ICCCI);2023-01-23

3. A survey on the latest FET technology for samsung industry;4TH INTERNATIONAL SCIENTIFIC CONFERENCE OF ALKAFEEL UNIVERSITY (ISCKU 2022);2023

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