Author:
Kanojia Ayush,Agrawal Sachin,Lorenzo Rohit
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Reference21 articles.
1. Vijayakumar, V., Ilayarajaa, K. T., Ravi, T. et al. (2021), Analysis of High Speed Hybrid Full Adder. 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS), (pp. 1641–1645).
2. Dokania, V., Verma, R., Guduri, M., et al. (2018). Design of 10T full adder cell for ultralow-power applications. Ain Shams Engineering Journal, 9(4), 2363–2372.
3. Parameshwara, M. C., & Srinivasaiah, H. C. (2017). Low-power hybrid 1-bit full adder circuit for energy efficient arithmetic applications. Journal of Circuits Systems and Computers, 26(1), 1–15.
4. Weste, N., & Harris, D. (2010). CMOS VLSI design: A circuits and systems perspective (4th ed.). Addison-Wesley.
5. Agrawal, P., Raghuvanshi, D. K., & Gupta, M. K. (2017). A low-power high-speed 16T 1-bit hybrid full adder. International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017, 348–352.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Optimizing the 12T Hybrid 1-Bit Full Adder Circuit for Low Energy Applications;2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
2. Design and Implementation of High Frequency 16-bit full adder on FPGA Families;2023 4th International Conference for Emerging Technology (INCET);2023-05-26