Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design-Reference-Cited by-同舟云学术

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Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Published:2023-11 Issue:1 Volume:133 Page:699-724
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Umadevi S.,Venkatesh Sruthi

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://link.springer.com/content/pdf/10.1007/s11277-023-10789-3.pdf

Reference28 articles.

1. Khailany, B., Krimer, E., Venkatesan, R., Clemons, J., Emer, J.S., Fojtik, M., Klinefelter, A., et al. (2018). A modular digital VLSI flow for high-productivity SoC design. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), IEEE, pp. 1–6.

2. Kamakshi, A.D., Fojtik, M., Khailany, B., Kudva, S., Zhou, Y. and Calhoun, B.H. (2016). Modeling and analysis of power supply noise tolerance with fine-grained GALS adaptive clocks. In 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 75–82.

3. Dai, H., Liu, Y., Niu, J. and Ou, P. (August 13, 2019). Static timing analysis in circuit design. U.S. Patent, 10, 380,285.

4. Blaauw, D., Zolotov, V., & Sundareswaran, S. (2002). Slope propagation in static timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(10), 1180–1195.

5. Chen, G., Onodera, H. and Tamaru, K. (1996). Timing and power optimization by gate sizing considering false path. In Proceedings of the Sixth Great Lakes Symposium on VLSI, IEEE, pp. 154–159.

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1. FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA Flows;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09

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