On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification

Author:

Cumplido René,Carrasco-Ochoa J. Ariel,Feregrino Claudia

Publisher

Springer Berlin Heidelberg

Reference9 articles.

1. Martínez-Trinidad, J.F., Guzmán-Arenas, A.: The logical combinatorial approach to pattern recognition an overview through selected works. Pattern Recognition 34(4), 741–751 (2001)

2. Lazo-Cortes, M., Ruiz-Shulcloper, J., Alba-Cabrera, E.: An overview of the evolution of the concept of testor. Pattern Recognition 34(4), 753–762 (2001)

3. Dmitriev, A.N., Zhuravlev, Y.I., Krendeliev, F.P.: About mathematical principles of objects and phenomena classification (In Russian). Diskretni Analiz 7, 3–15 (1966)

4. Spartan-3 Data sheet, Available at http://www.xilinx.com

5. Gomez, M.: Hardware-in-the-Loop Simulation. Embedded Systems Programming 14(13) (December 2001)

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2. A fast hardware software platform for computing irreducible testors;Expert Systems with Applications;2015-12

3. Hardware–software platform for computing irreducible testors;Expert Systems with Applications;2012-02

4. A Fast Implementation for the Typical Testor Property Identification Based on an Accumulative Binary Tuple;International Journal of Computational Intelligence Systems;2012

5. FPGA-Based Architecture for Computing Testors;Intelligent Data Engineering and Automated Learning - IDEAL 2007;2007

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