Author:
Zhang Qinhai,Trullemans Charles
Reference16 articles.
1. M.S. Abadir, J. Ferguson, T.E. Kirkland: Logic Design Verification via Test Generation. IEEE Trans. on CAD Vol. 7, No. 1, Jan. 1988, pp. 138–148
2. G.D. Hachtel, R.M. Jacoby: Verification Algorithms for VLSI Synthesis. IEEE Trans. on CAD, Vol. 7, No. 5, MAY, 1988, pp. 616–640
3. R.E. Bryant: Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. on Computers Vol C-35, No. 8, Aug. 1986, pp. 677–691
4. S. Malik, A.R. Wang, R.K. Brayton, A. Sangiovanni-Vincentelli: Logic Verification Using Binary Decision Diagram in a Logic Synthesis Environment Proc. ICCAD-88, 1988, pp. 6–9
5. S. Minato, N. Ishiura: Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation. Proc. 27th DAC, 1990, pp. 52–57
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