Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study-Reference-Cited by-同舟云学术

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Enhancing Performance of Dual-Gate FinFET with High-K Gate Dielectric Materials in 5 nm Technology: A Simulation Study

Published:2023-10-04 Issue:6 Volume:24 Page:557-569
ISSN:1229-7607
Container-title:Transactions on Electrical and Electronic Materials
language:en
Short-container-title:Trans. Electr. Electron. Mater.

Author:

Rao M. V. Ganeswara,Ramanjaneyulu N.,Pydi Balamurali,Soma Umamaheshwar,Babu K. Rajesh,Prasad Satti Harichandra

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s42341-023-00473-5.pdf

Reference31 articles.

1. L. Artola, M. Gaillardin, G. Hubert, M. Raine, P. Paillet, Modeling single event transients in advanced devices and ICs. IEEE Trans. Nucl. Sci. 62(4), 1528–1539 (2015)

2. T. Dutta, S. Kumar, P. Rastogi, A. Agarwal, Y.S. Chauhan, Impact of channel thickness variation on bandstructure and source-to-drain tunneling in ultra-thin body III–V MOSFETs. IEEE J. Electron Devices Soc. 4(2), 66–71 (2016)

3. A.S. Roy, S.P. Mudanai, D. Basu, M.A. Stettler, Compact model for ultrathin low electron effective mass double gate MOSFET. IEEE Trans. Electron Devices 61(2), 308–313 (2014)

4. Z. Ren, R. Venugopal, S. Goasguen, S. Datta, M.S. Lundstrom, NanoMOS 2.5: a two-dimensional simulator for quantum transport in double-gate MOSFETs. IEEE Trans. Electron Devices 50(9), 1914–1925 (2003)

5. C. Yadav, J.P. Duarte, S. Khandelwal, A. Agarwal, C. Hu, Y.S. Chauhan, Capacitance modeling in III–V FinFETs. IEEE Trans. Electron Devices 62(11), 3892–3897 (2015)

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