A shift register architecture for high-speed data sorting-Reference-Cited by-同舟云学术

A shift register architecture for high-speed data sorting

Published:1995-12 Issue:3 Volume:11 Page:273-280
ISSN:0922-5773
Container-title:Journal of VLSI signal processing systems for signal, image and video technology
language:en
Short-container-title:Journal of VLSI Signal Processing

Author:

Lee Chen -Yi,Tsai Jer -Min

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Information Systems,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/BF02107058.pdf

Reference9 articles.

1. R. Sedgewich,Algorithms in C, Addison Wesley, 1990.

2. A.L. Fisher, “Systolic Algorithm for Running Order Statistics,” inSignaland Image Processing, Dept. Comp. Science, Carnegie Mellon Univ., Pittsburgh, July 1981.

3. E. Ataman, V.K. Aatre, and K.M. Wong, “A Fast Method for Real-Time Median Filtering,”IEEE Trans. on ASSP, Vol. ASSP-23, pp. 552–557, Dec. 1975.

4. V.V. Bapeswara Rao and K. Sankara Rao, “A New Algorithm for Real-Time Median Filtering,”IEEE Trans. on ASSP, Vol. ASSP-34, No. 6, Dec. 1986.

5. S.Y. Kung, P.S. Lewis, and S.C. Lo, “On Optimally Mapping Algorithms to Systolic Arrays With Applications to the Transitive Closure Problem,”Proc. IEEE Circuits and Systems, San Jose Ca. pp. 1316–1322, May 1986.

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