UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing
Author:
Publisher
Springer Science and Business Media LLC
Subject
Artificial Intelligence,Industrial and Manufacturing Engineering,Software
Link
http://link.springer.com/content/pdf/10.1007/s10845-009-0298-2.pdf
Reference21 articles.
1. Buckley J. D., Karatzas C. (1989) Step and scan: A system overview of a new lithography tool. Proceedings of SPIE: Optical/Laser Microlithography II 1088: 424–433
2. Chien C.-F., Chang K.-H., Chen C.-P. (2003) Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing. International Journal of Production Research 41(11): 2547–2561
3. Chien C.-F., Hsu C.-Y. (2006) A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing. Journal of Intelligent Manufacturing 17(4): 429–440
4. Chien C.-F., Wang H.-J., Wang M. (2007) A UNISON framework for analyzing alternative strategies of IC final testing for enhancing overall operational effectiveness. International Journal of Production Economics 107(1): 20–30
5. Chien C.-F., Wu J.-Z. (2003) Analyzing repair decisions in the site imbalance problem of semiconductor test machines. IEEE Transactions on Semiconductor Manufacturing 16(4): 704–711
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