Layout and Technology Influences on ESD Protection Circuit Design

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Publisher

Kluwer Academic Publishers

Reference32 articles.

1. Wang, A. Z., Feng, H. G., Gong, K., Zhan, R. Y. and Stine, J., “On-Chip ESD Protection Design for Integrated Circuits: an Overview for IC Designers”, J. Microelectronics, Elsevier Science, Vol. 32/9, August 2001, pp.733–747.

2. Amerasekera, A. and Duvvury, C., ESD in Silicon Integrated Circuits, John Wiley & Sons, England, 1995.

3. Dabral, S. and Maloney, T., Basic ESD and I/O Design, John Wiley & Sons, 1998.

4. Feng, H. G., “A Mixed-Mode Simulation-Design Methodology for on-Chip ESD Protection Design”, MS Thesis, Illinois Institute of Technology, May 2001.

5. Rountree, R. and Hutchins, C., “NMOS Protection Circuitry”, IEEE Trans. Elec. Dev., ED-32, 1985, pp.910–917.

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