A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits

Author:

Andreatta Alexandre A.,Ribeiro Celso C.

Publisher

Springer Science and Business Media LLC

Subject

Management Science and Operations Research,General Decision Sciences

Reference36 articles.

1. A.A. Andreatta, A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits, M.Sc. Dissertation, Department of Electrical Engineering, Catholic University of Rio de Janeiro (1994), in Portuguese.

2. E.C. Archambeau and E.J. McCluskey, Fault coverage of pseudo-exhaustive testing,Digest of Papers of the 14th Int. Conf. on Fault-Tolerant Computing (IEEE, 1984) pp. 141–145.

3. Z. Barzilai, D. Coppersmith and A.L. Rosenberg, Exhaustive generation of bit patterns with applications to VLSI self-testing, IEEE Trans. Computers C-32(1983)190–193.

4. F. Berglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator inFortran, Paper presented at the special session onATPG and Fault Simulation, Int. Symp. on Circuits and Systems, Kyoto (IEEE, 1985).

5. Z. Barzilai, J. Savir, G. Mankowsky and M.G. Smith, The weighted syndrome sums approach to VLSI testing, IEEE Trans. Computers C-30(1981)996–1001.

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