Affiliation:
1. School of Computer Studies, University of Leeds, Leeds, UK
Abstract
Abstract
Conditions necessary to produce correct asymptotic complexity results and realistic performance estimates for VLSI devices, using discrete high-level VLSI complexity models, are examined. A set of design constraints is formulated, based on results from two experiments involving suitably designed and fabricated VLSI devices. The basis of the complexity model is modified so that it satisfies the constraints. A case-study for an integer multiplier design shows that the modified model produces asymptotic results in agreement with empirical measurements. Low-level performance estimates are then obtained using the RC network delay model in conjunction with the VLSI complexity model.
Publisher
Association for Computing Machinery (ACM)
Subject
Theoretical Computer Science,Software