Practical Architectures for High-Speed Clock Recovery and Data Retiming
Author:
Publisher
Springer US
Link
http://link.springer.com/content/pdf/10.1007/978-1-4615-2243-0_5
Reference19 articles.
1. Hans Ransijn and Paul O’Connor. A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC. IEEE J. Solid-State Circuits, 26(10):1345–1353, October 1991.
2. Kazuo Hagimoto, Yuuzou Miyagawa, Yutaka Miyamoto, Masanobu Ohhata, Tatsuhito Suzuki, and Hiroyuki Kikuchi. Over 10 Gb/s regenerators using monolithic IC’s for lightwave communication systems. IEEE J. Select. Areas Commun., SAC-9(5):673–682, June 1991.
3. Peter Wennekers, Ulrich Novotny, Axel Huelsmann, Gugrun Kaufel, Klaus Koehler, Brian Raynor, and Joachim Schneider. 10-Gb/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/A1GaAs technology. IEEE J. Solid-State Circuits, 27(10):1347–1352, October 1992.
4. Robert R. Cordell, J. B. Forney, Charles N. Dunn, and William G. Garrett. A 50 MHz phase-and frequency-locked loop. IEEE J. Solid-State Circuits, SC-14(6):1003–1010, December 1979.
5. Donald Richman. Color-carrier reference phase synchronization accuracy in NTSC color television. Proc. IRE, 42:106–133, January 1954.
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