Author:
Gaillardon Pierre-Emmanuel,O’Connor Ian,Clermidy Fabien
Reference37 articles.
1. M. Lin, A. El Gamal, Y.-C. Lu, S. Wong, Performance benefits of monolithically stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), 216–229 (2007)
2. E. Ahmed, J. Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(3), 288–298 (2004)
3. T. Ye, L. Benini, G. De Micheli, Packetization and routing analysis of on-chip multiprocessor networks. J. Syst. Architect. 50(2–3), 81–104 (2004)
4. D.L. Lewis, S. Yalamanchili, H.-H. S. Lee, High performance non-blocking switch design in 3D die-stacking technology. In:Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, (2009), pp. 25–30
5. H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez, Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. In:International Conference on Computer-Aided Design (ICCAD’2006), November 2006, pp. 675–679