Packetization and routing analysis of on-chip multiprocessor networks

Author:

Ye Terry Tao,Benini Luca,Micheli Giovanni De

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference31 articles.

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3. A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, D. Lindqvist, Network on chip: an architecture for billion transistor era, Proceeding of the IEEE NorChip Conference, November 2000, pp. 166–173

4. W. Dally, B. Toles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference, June 2001, pp. 684–689

5. Networks on chips: a new SoC paradigm;Benini;IEEE Computer,2002

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