1. A. Agarwal, M. Horowitz, and J. Hennessy, “An analytical cache model,” ACM Trans. Computer Systems, vol. 7, pp. 184–215, May 1989.
2. J. Archibald and J.-L. Baer, “Cache coherence protocols: Evaluation using a multiprocessor simulation model,” ACM Trans. Comput. Sys., vol. 4, pp. 273–298, Nov. 1986.
3. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, MA: McGraw-Hill (MIT Press), 1990.
4. T. M. Conte, “Systematic computer archiecture prototyping,” Ph.D. dissertation, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL, 1992.
5. I. J. Haikala, “Cache hit ratios with geometric task switch intervals,” in Proc. 11th Ann. Int’l Symp. Computer Architecture, (Ann Arbor, MI), pp. 364–371, June 1984.