Author:
Chen Mingsong,Qin Xiaoke,Koo Heon-Mo,Mishra Prabhat
Reference37 articles.
1. Barnhart C, Brunkhorst V, Distler F, Farnsworth O, Ferko A, Keller B, Scott D, Koenemann B, Onodera T (2002) Expending OP-MISR beyond 10x scan test efficiency. IEEE Des Test Comput 19(5):65–73
2. Campenhout D, Mudge T, Hayes J (1999) High-level test generation for design verification of pipelined microprocessors. In: Proceedings of design automation conference (DAC), pp 185–188
3. Chandra A, Chakrabarty K (2001) System-on-a-Chip test data compression and decompression architectures based on golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368
4. Chandra A, Chakrabarty K (2003) Test data compression and dtest resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Comput 52(8):1076–1088
5. Cheng K, Krishnakumar S (1996) Automatic generation of functional vectors using the extended finite state machine model. ACM Trans Des Autom Electron Syst 1(1):57–79