Author:
Mandal Ayan,Khatri Sunil P.,Mahapatra Rabi N.
Reference21 articles.
1. N. R. Adiga, M. A. Blumrich, D. Chen, P. Coteus, A. Gara, M. E. Giampapa, P. Heidelberger, S. Singh, B. D. Steinmacher-Burow, T. Takken, M. Tsao, and P. Vranas, “Blue Gene/L torus interconnection network,” IBM J. Res. Dev., vol. 49, no. 2, pp. 265–276, Mar. 2005.
2. O.T.-C. Chen and R.R.-B. Sheen, “A power-efficient wide-range phase-locked loop,” Solid-State Circuits, IEEE Journal of, vol. 37, no. 1, pp. 51–62, Jan 2002.
3. W. J. Dally and C. L. Seitz, “The Torus Routing Chip,” The Journal of Distributed Computing, vol. 1(3), pp. 187–196, 1986.
4. W.J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Design Automation Conference, 2001. Proceedings, 2001, pp. 684–689.
5. Jose Duato, Sudhakar Yalamanchili, and Ni Lionel, Interconnection Networks: An Engineering Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2002.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献