1. Further details about these studies can be obtained through the World Wide Web via URL www.cs.indiana.edu. Access the Single Pulser Study through the Hardware Methods Group thread in the list of departmental research projects. Individuals wishing to contribute to this collection should contact sjohnson@cs.indiana.edu or write Hardware Methods Laboratory, Indiana University Computer Science Department, Bloomington Indiana, USA.
2. Bhaskar Bose. DDD — A Transformation system for Digital Design Derivation. Technical Report 331, Computer Science Dept. Indiana University, May 1991.
3. J.R. Burch, E.M. Clarke, D.L. Dill, and K. L. McMillan. Sequential circuit verification using symbolic model checking. In Proceedings of the 27th ACM/IEEE Design Automation Conference, June 1990.
4. E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finitestate concurrent systems using temporal logic specification. ACM Transactions on Programming Languages and Systems, 8(2), April 1986.
5. Kathi Fisler. Extending formal reasoning with support for hardware diagrams, 1994. This volume.