A new distributed congestion control mechanism for networks on chip
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s11235-009-9257-7.pdf
Reference20 articles.
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3. Shin, D., Gerstlauer, A., Dömer, R., & Gajski, D. D. (2005). Automatic network generation for system-on-chip communication design. In CODES+ISSS 2005 (pp. 255–260).
4. Goossens, K., Dielissen, J., & Radulescu, A. (2005). Æthereal network on chip: concepts, architectures and implementations. IEEE Design and Test of Computers, 22(5), 414–421.
5. Guerrier, P., & Greiner, A. (2000). A generic architecture for on-chip packet-switched interconnections. In Proceedings of the design automation and test in Europe (DATE) (pp. 250–256) 2000.
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