1. G. Campardo, R. Micheloni, D. Novosel, VLSI-Design of Non-Volatile Memories (Springer, 2005)
2. S. Lee et al., A 128 Gb 2b/cell NAND flash memory in 14 nm technology with tprog = 640 μs and 800 MB/s I/O Rate, in 2016 IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco, USA, Feb 2016, pp. 138–139
3. N. Chan, M.F. Beug, R. Knoefler, T. Mueller, T. Melde, M. Ackermann, S. Riedel, M. Specht, C. Ludwig, A.T. Tilke, Metal control gate for sub-30 nm floating gate NAND memory, in Proceedings of 9th NVMTS, Nov 2008, pp. 82–85
4. R. Micheloni, L. Crippa, A. Marelli, Inside NAND Flash Memories, Chap. 6 (Springer, 2010)
5. K.-D. Suh et al., A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J. Solid-State Circ. 30(11), 1149–1156 (1995)