Author:
Mansureh Moghaddam Shahraki,Cho Jae-Min,Choi Kiyoung
Reference117 articles.
1. Ahn M, Yoon J, Paek Y, Kim Y, Kiemb M, Choi K (2006) A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In: Proceedings of the design, automation and test in Europe, DATE ’06, vol 1, p 6
2. Altera arria 10 FPGA.
www.altera.com
. Accessed 28 Nov 2015
3. Aletà A, Codina JM, Sánchez J, González A (2001) Graph-partitioning based instruction scheduling for clustered processors. In: Proceedings of the 34th annual ACM/IEEE international symposium on microarchitecture, MICRO 34. IEEE Computer Society, Washington, DC, pp 150–159
4. Altera stratix v FPGA.
www.altera.com
. Accessed 28 Nov 2015
5. Ansaloni G, Bonzini P, Pozzi L (2011) EGRA: a coarse grained reconfigurable architectural template. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(6):1062–1074
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