ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing
Author:
Publisher
Springer Science and Business Media LLC
Subject
Information Systems
Link
http://link.springer.com/content/pdf/10.1007/s11554-008-0084-y.pdf
Reference37 articles.
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2. Vogt, T., Wehn N.: A reconfigurable application specific instruction set processor for Viterbi and Log-MAP decoding. IEEE Workshop Signal Proc Syst Des Impl, pp. 142–147 (2006)
3. Dinoi, L., Martini, R., Masera, G., Quaglio, F., Vacca, F.: ASIP design for partially structured LDPC codes. Electron Lett 42(18), 49–50 (2006)
4. Momcilovic, S., et al.: Application specific instruction set processor for adaptive video motion estimation. In: Proceedings of IEEE Euromicro DSD 160–167 (2006)
5. Bajot, Y., Mehrez, H.: Customizable DSP architecture for ASIP core design. In: Proceedings of ISCAS’01, pp 302–305 (2001)
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