Network on Chip Aspects-Reference-Cited by-同舟云学术

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Network on Chip Aspects

Published:2015 Issue: Volume: Page:11-44
ISSN:
Container-title:Analysis and Design of Networks-on-Chip Under High Process Variation
language:
Short-container-title:

Author:

Ezz-Eldin Rabab,El-Moursy Magdy Ali,Hamed Hesham F. A.

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-25766-2_2

Reference58 articles.

1. Öberg J (2003) Clocking strategies for networks-on-chip. Kluwer Academic Publishers, New York, pp 153–172

2. Friedman EG (2001) Clock distribution networks in synchronous digital integrated circuits. IEEE J 89(5):665–692

3. Mu F, Svensson C (1999) self-tested self-synchronization for parallel systems. IEEE Trans Parallel Distrib Syst J 10(8):769–780

4. Mu F, Svensson C (2001) Self-tested self-synchronization circuit for mesochronous clocking. IEEE Trans Circuits Syst II 48(2):129–140

5. Söderquist I (2003) Globally updated mesochronous design style. IEEE J Solid-State Circuits 38(7):1242–1249

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Elastic buffer evaluation for link pipelining under process variation;IET Circuits, Devices & Systems;2018-05-15

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