A Methodology for the Characterisation of Leakages in Combinatorial Logic-Reference-Cited by-同舟云学术

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A Methodology for the Characterisation of Leakages in Combinatorial Logic

Published:2016 Issue: Volume: Page:363-382
ISSN:0302-9743
Container-title:Security, Privacy, and Applied Cryptography Engineering
language:
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Author:

Bertoni Guido,Martinoli Marco

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-49445-6_21

Reference17 articles.

1. Bertoni, G., Daemen, J., Peeters, M., Assche, G.V.: Building power analysis resistant implementations of Keccak. In: Second SHA-3 Candidate Conference (2010)

2. Lecture Notes in Computer Science;G Bertoni,2013

3. Lecture Notes in Computer Science;B Bilgin,2014

4. Lecture Notes in Computer Science;B Bilgin,2014

5. Brzozowski, J., Ésik, Z.: Hazard algebras. Formal Methods Syst. Des. 23(3), 223–256 (2003)

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1. Side Channel Analysis and Evaluation on Cryptographic Products;J ELECTRON INF TECHN;2020

2. Towards efficient and automated side-channel evaluations at design time;Journal of Cryptographic Engineering;2020-06-22

3. A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs;Integration;2020-01

4. Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-12

5. Formal Verification of Masked Hardware Implementations in the Presence of Glitches;Advances in Cryptology – EUROCRYPT 2018;2018

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